1. Technical Field
The present invention generally relates to a phase-locked loop (PLL), and more particularly, to a digital PLL (DPLL) and a digital phase-frequency detector (DPFD) thereof.
2. Description of Related Art
With the rapid development of wireless communication, the digital phase-locked loop (DPLL) is one of important technologies in current years since it is easy to be realized in advanced system on chip. However, it is a challenge to design a DPLL having fast settling and low noise.
Currently, the DPLL faces two main issues: (1) after being digitalized, is the phase noise of the DPLL lower than that of a conventional phase-locked loop (PLL)? (2) does it provide wideband phase modulation or fast settling? Accordingly, it is a tradeoff between loop bandwidth and phase noise of the DPLL. For the DPLL, a larger loop bandwidth helps to reduce locking time and phase noise of the digitally controlled oscillator (DCO). Especially, when the DPLL is unlocked, if the loop bandwidth is timely exchanged, the locking time is reduced, such as U.S. Pat. No. 6,851,493 and U.S. patent publication No. 2008/0315960. These techniques necessarily depend on external apparatuses, so as to generate control signals to change the loop bandwidth.
Moreover, although the larger loop bandwidth helps to reduce locking time and phase noise of the DCO, a higher resolution digital phase-frequency detector (DPFD) is required to reduce in-band phase noise. For example, if the phase noise is lower than 100 dBc/Hz, the resolution of the DPFD is required up to 6 ps (picoseconds). Accordingly, the time required for being analyzed ranges from the pulse width of the reference frequency, such as 40 ns (nanoseconds), to 6 ps. However, if some apparatuses are added into the DPFD, the said issue is improved. As a result, when the DPLL is unlocked, the DPFD has lower resolution, but when the DPLL is locked, the resolution of the DPFD is highly raised, such as the paper “A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation” (IEEE JSSCC, vol. 43, no. 12, pp. 2776-2786, December 2008) published by C.-M. Hsu, M. Z. Straayer, and M. H. Perrott. However, the published technique is complex. The divisor of the divider, i.e. the divide scale thereof, is required to be changed to maintain a constant output frequency.